Time Domain Constraints on Switching with Gated-GND Cache Structures for Static Power Reduction

As semiconductor technology goes into the deep submicron region, the static power caused by leakage current is no longer negligible. Gated-GND circuit technique switches SRAM cells into standby mode to reduce the static power. In this paper, we studied the detailed current scenario in a Gated-GND circuit structure. Based upon the analysis, we employed a more accurate way to estimate the efficiency of the GatedGND technique and found that the efficiency is dependant on the length of the standby mode period. Thus we further proposed a time-domain constraint for using this circuit technique in higher level switchingbased power reduction algorithms. Simulation shows the standby mode length should be no less than 0.175ms for a TSMC 180nm technology so as to achieve significant power reduction.